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Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All

information discussed herein is provided on an “as is” basis, without warranties of any kind.

TN-29-71: Enabling Software BCH ECC on a Linux Platform

Introduction

PDF: 09005aef8492449f/Souce: 09005aef849244ab Micron Technology, Inc., reserves the right to change products or specifications without notice.

tn2971_software_bch_ecc_on_linux.fm - Rev. B 4/12 EN

Technical Note

Enabling Software BCH Error Correction Code (ECC) on a Linux Platform

Introduction

Many current designs are moving to NAND Flash memory to take advantage of its higher

densities and lower cost for high-performance applications. However, a NAND Flash

device may have bad blocks that require error correction code (ECC) to maintain data

integrity.

Most new processor designs anticipate coupling with NAND Flash devices and include

4-bit and greater ECC engines within the hardware itself. However, some existing

processor designs only support 1-bit ECC. This document addresses applications using

these existing 1-bit ECC processors to enable Micron

MT29F1GxxABxDA,

MT29F2GxxABxEA, MT29F4GxxABxDA, and MT29F1GXXABXEA NAND Flash memory

devices with software BCH ECC.

Micron Single-Level Cell (SLC) NAND Error Management Requirements

NAND Flash memory requires ECC to ensure data integrity. Error management require-

ments for Micron’s MT29F1GxxABxDA, MT29F2GxxABxEA, and MT29F4GxxABxDA

NAND Flash memory devices are described in Table 1. Requirements for

MT29F1GxxABxEA NAND are described in Table 2. Each SLC device includes 4-bit on-

die ECC.

Table 1: ECC Requirements for MT29F1GxxABxDA, MT29F2GxxABxEA, and MT29F4GxxABxDA

Description Requirement

Minimum ECC required 4-bit ECC per 528 bytes

Minimum ECC with internal ECC enabled 4-bit ECC per 516 bytes (user data) plus 8

bytes (parity data)

Minimum ECC required for block 0 if

PROGRAM/ERASE cycles are less than 1000

1-bit ECC per 528 bytes

Table 2: ECC Requirements for MT29F1GxxABxEA

Description Requirement

Minimum ECC required 4-bit ECC per 528 bytes

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Summary of Contents

Page 1 - Technical Note

Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Produc

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