MTD PS Specifications

USERS MANUAL Revision 8.0 MTD/PS-0215 January 2, 2008 KODAK KAF SERIES CCD DIGITAL REFERENCE EVALUATION BOARD USERS MANUAL

J1, J2 IMAGER BOARD CONNECTORS CCD Daughter Boards plug into these connectors. The daughter boards route the clock and bias traces from the timing b

BOARD REQUIREMENTS: POWER SUPPLY The board requires only a single +5V, 1.5 Amp or greater power supply to operate. An on board switching power supply

CONFIGURATION MODES The following modes of operation are available to the user: LINE/SWITCHES MODES The Line/Switches Jumper (SW5) Selects whether s

AD_IN/EX MODES The board comes with an Analog Devices AD9816 12 bit A/D converter on board. This A/D has several features, such as multiple configur

ADJUSTMENTS Adjustments can be made to the A/D registers during operation of the board by utilizing the DATA dipswitch (SW10), the ADDRESS switch (S

POWER SUPPLY MODES Power can be supplied to the board in one of two ways: Switching Power Supply The board comes supplied with a 500 kHz switching

CCD IMAGER BOARDS Each CCD has an imager board. The imager boards route the bias voltage traces from the timing board through connectors J1 and J2 to

OUTPUT SELECTION FOR SENSORS WITH TWO OUTPUTS The KAF-1001E, KAF-0261E, and KAF-4301E sensors have two video outputs. The outputs have different gai

TIMING FIXED TIMING: H1, H2 VARIABLE TIMING: V1, V2 (binning modes) RESET (binning modes) CLAMP (binning modes) SAMPLE (binning modes) A/D Clock (bin

FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA Figure 1: System Block Diagram GuardVOGVSS, VLGVSUB1200 pFCDSCLK1CDSCLK2ADCCLK12 BitsAD98161K

TABLE OF CONTENTS Introduction...

©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p20 Power ONCLEAR_ALLSET-UPINITIALIZESTILL/FREE-RUN?IMAGEACQUIRE?INT

Address Register Function Default Programming 0 Configuration Register bit 7 MSB test mode bit always 0 0 bit 6 test mode bit always 0

Switches witches Select wh ol of modes comeLine/S ere contr s from Switch_Int[5..0] Integration timing control lines Switch_Bin[2..0] Binning

C Sett /Frame CD Switch ing CCD Pixels/Line Lines0 Mode1 or KAF-1680 2 * Test 1E/LE 1001 1E 1500 1200 KAF-1402 ode 2 4 Test M 10 3 KAF-1

Bin Switch (SW2) Setting Binning Mode 1 1x1 (No Binning) 2 1x1 (No Binning) 3 1x1 (No Binning) 4 1x1 (No Binning) 5 1x1 (No Binning) 6 1x1 (No

SW7 Swit(Coarse) itch(Coarse) ration Time onds) ch Setting INT 5-3 Sw Integ(Sec0 000 0 1 001 1 2 010 2 3 011 3 4 100 4 5 101 5 6 110 7 7 111 9

VideoVsatVdark+VoffsetVpixResetH1H21 count = 8tClamp Figure 4: Pixel Rate Timing Note: The KAF-4301E implements 16t = 1pixel and 32t = 1 pixel modes

Integration Time V1 V2 H1H2ClampSampleA/D clkLINE*RPIX*FRAME*64 tt = 1/system clock (Default Setting = 200ns)5t64 t64 t2t50t12t140t25t222t Figure 5:

Integration Time V2 V1 H2H1ClampSampleA/D clkLINE*RPIX*FRAME*100 tt = 1/system clock (Default Setting = 200ns)4t100 t100 t2t50t248t25t329t Figure 6:

Frame Timing (KAF 0261,0401,1001,1302,1401,1602,2001,4202,4300,6303,16800)tReadoutLine 0 1N-1 N1 Frame = N LinesIntegration Time V1 V2 H1H2ClampSampl

Output Selection for Sensors with Two Outputs ...

Frame Timing (KAF3040, KAF 3200)tReadoutLine 0 1N-1 N1 Frame = N LinesIntegration Time V2 V1 H2H1ClampSampleA/D clkLINE*RPIX*FRAME* Figure 8: Frame

VideoVsatVdark+VoffsetVpixResetH2H11 count = 8tClampSampleA/D clockPIX1t1t3t8t3tt = 1/system clock (Default Setting = 200ns)4t Figure 9: Pixel Rate

Still Mode: Flush and Integration TimingLine 0Integration Time V1 V2LINE*PIX*FRAME*Line NCCD Readout TimeFlush TimingT = 128t4000 TIMAGE ACQUIRE5t66t

VideoVpixbinnedResetH1H21 count = 8*(bin mode)*tClampSampleA/D clockPIX1t1t8t3tt = 1/system clock(Default Setting =200ns)4t3tPixel Rate Timing Figure

Linearity0200004000060000800001000001200001400001600001800000 2000 4000 6000 8000 10000Integration Time (ms)Electron sLinearity Cu rveFull Well = 11

SYSTEM NOISE FLOOR VS. OPERATING FREQUENCY Frequency (MHz) Noise Floor (Electrons) Dynamic Range* (Bits) Dynamic Range* (dB) El/ADU System Gain 1 40

Linearity of Programmable Analog Gain02004006000 15 30 45 75 90 105 120 150 165 180 195 225 255Programmable Gain CodeA/D Units80060 135 210 240PGA G

CONNECTOR PINOUTS Imager Board Connectors J1, J2 Connector Pin Assignment Connector Pin Assignment J1 1 N.C. J2 1 VSUB J1 2 VSUB J2 2

Input Connector J6 Pin Assignment Pin Assignment 1 INT0 2 GND 3 INT 4 D 2 GN5 6 INT3 GND7 INT 8 GND 5 9 IMAGE_ACQUIRE 10 GND 11 BI 12 GN

Output Connector J4 ector Assignment Comment Conn Pin J4 DIG0+ 1 RS422 J4 DIG0- 2 RS422 J4 DIG1+ 3 RS422 J4 DIG1- 4 RS422 J4 GND 5 J4 6

TABLE OF TABLES Table 1: Board Inputs, Outputs, Switches...

Integrate Sync Connector J7 r Assignment Connecto Pin Comment J7 1 Integrate TTL J7 2 GND Power Connector J5 Assignment Connector PinJ5

REFERENCES Analog Devices AD9816 Specification Sheet Linear Technology LT1372 Sp heKAF Series Device Performan SpecificatioS Application Note on KAF

APPENDIX APPENDIX1: PART NUMBER AVAILABILITY This appendix may be updated independent of the performance specification. y for the latest revision.

APPENDIX 2: PARTS LIST E QTY. BOARD REFERENCE # MANUFACTURER PART DESCRIPTION PACKAGBLM11P600SPT FERRITE FERRITE 0603 51 FB1-15, FB17-18, FB20-

CRCW0603-1002-FT 10K OHM 1% RES 0603 25 R1-5, R20, R24-27, R30-31, R48, R52, R61-62, R64, DALE R68, R70, R72-76, R78 4310R-101-103 10K SIP 1

5-826632-0 BREAKAWAY STRIP HEADER 24 2 J1,J2 AMP 5-826632-0 BREAKAWAY STRIP HEADER 10 1 J8 AMP 5-826632-0 BREAKAWAY STRIP HEADER 2 1 AM

APPENDIX 3: IMAGER BOARD SCHEMATICS ©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p46

INTRODUCTION The Kodak Digital Science TM KAF Series CCD Digital Reference Evaluation Board provides a powerful platform to quickly and easily implem

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©Eastman Kodak Company, 2008. Kodak and Pixelux are trademarks.

SPECIFICATIONS Maximum Data Rate 6MHz Resolution 12 Bits Frame Rate Depends on Data Rate, CCD Array size, and Integration time. OUTPUTS: D[

ARCHITECTURE OVERVIEW A complete Block Diagram of the CCD Digital Reference Evaluation Board is shown in . MASTER CLOCK The Master Clock runs at eig

CCD BIAS VOLTAGES CCD bias voltages (VRD, VOG, VLG) are supplied by filtered outputs of adjustable potentiometers. Fixed CCD bias voltages (LOD, VSS

UNIT INTEGRATION TIME Integration Timing: The amount of time the CCD is exposed to light before clocking out the accumulated charge is called the in